Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor

ABSTRACT

The present invention relates to a method of forming a very shallow source-drain (S/D) extension while simultaneously highly doping a very narrow polysilicon gate through to the gate dielectric interface. The invention also relates to the resulting semiconductor.

BACKGROUND OF THE INVENTION

[0001] 1. Technical Field

[0002] The present invention relates generally to methods of fabricatingsemiconductor wafers. More particularly, the present invention relatesto a method of forming a very shallow source-drain (S/D) extension whilesimultaneously doping a very narrow polysilicon gate. The presentinvention also includes the resulting semiconductor.

[0003] 2. Related Art

[0004] Heretofore, demand for higher performance chips have driven MetalOxide Semiconductor Field Effect Transistors (MOSFET) to shorter channellength for higher current. This high performance requires a shallowsource-drain (S/D) extension and highly doped polysilicon gatescompletely through to the gate dielectric interface. However, aspolysilicon width becomes narrower, with the aspect ratio close to 1,optimum doping of the polysilicon gate by conventional ion implantationafter gate definition etching becomes very difficult.

[0005] As a result, there exists a need to have processes of fabricationin which highly doped polysilicon gates can be created with very shallowS/D extensions.

SUMMARY OF THE INVENTION

[0006] The present invention is a method of providing a layer (e.g., asubstrate) including at least one polysilicon gate and at least onesource/drain region; and simultaneously doping at least one gate stackand the source-drain regions. As a result, very shallow S/D extensions(i.e., less than 0.1μ) can be created without extra lateral scatteringof dopant while at the same time providing a narrow (i.e., less than0.2μ), highly doped polysilicon gate (i.e., greater than 10¹⁹ atoms ofdopant/cm³) completely through to the gate dielectric interface.

[0007] The present invention also includes the resulting semiconductorexhibiting the very shallow S/D extensions and the highly dopedpolysilicon gate through to the gate dielectric interface.

[0008] The foregoing and other features and advantages of the inventionwill be apparent from the following more particular description ofpreferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The preferred embodiments of this invention will be described indetail, with reference to the following figures, wherein likedesignations denote like elements, and wherein:

[0010]FIG. 1 shows a semiconductor wafer prior to doping in accordancewith the present invention;

[0011]FIG. 2 shows a method of doping in accordance with a firstembodiment of the present invention;

[0012]FIG. 3 shows a method of doping in accordance with a secondembodiment of the present invention;

[0013]FIG. 4 shows a method of doping in accordance with a thirdembodiment of the present invention;

[0014]FIG. 5 shows a structure after forming deep S/D diffusions inaccordance with an alternative step of the present invention;

[0015]FIG. 6 shows a completed semiconductor in accordance with thepresent invention;

[0016]FIG. 7 shows a first step in a method of doping in accordance witha fourth embodiment of the present invention; and

[0017]FIG. 8 shows a second step in the method of doping in accordancewith the fourth embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Although certain preferred embodiments of the present inventionwill be shown and described in detail, it should be understood thatvarious changes and modifications may be made without departing from thescope of the appended claims. The scope of the present invention will inno way be limited to the number of constituting components, thematerials thereof, the shapes thereof, the relative arrangement thereof,etc., and are disclosed simply as an example of the preferredembodiments. In particular, the present invention has been disclosed foruse in high performance logic technology. However, the present inventioncan also be used to dope gates and S/D extensions of a high densityNon-Volatile Random Access Memory (NVRAM) device or other devices.

[0019]FIG. 1 is a cross-sectional view of a high performanceComplementary Metal-Oxide Semiconductor (CMOS) device 10 after deviceisolation formation, N-well and P-well formation and gate stackformation in accordance with conventional techniques but prior to dopingin accordance with the present invention. The device generally includesat this point of the manufacturing process: a silicon layer or substrate12 having located in a surface thereof a plurality of shallow trenchisolations (STI) 14, e.g., 0.3μ-0.4μ deep. The wells 16, 18 of thedevice 10 are located between the isolation trenches 14. The deviceincludes a P-well 16 and an N-well 18.

[0020] The polysilicon gate stacks 20 are also present at this junctureof manufacturing. The gate stacks 20 generally include a gate dielectriclayer 22, e.g., silicon dioxide, and a polysilicon body or gate 24 overthe wells 16, 18. On an upper surface of the polysilicon gates 24, alayer of gate wiring material 26 may also be provided prior to gatestack etching to replace the need to form titanium salicide later. Thiswiring material can be any highly conductive material, e.g., tungsten(W) or tungsten silicide (WSi_(x)).

[0021] At this juncture, in accordance with the present invention, thepolysilicon gates 24 are doped simultaneously with the source/drain(SID) regions.

[0022] As shown in FIG. 2, in a first embodiment of the presentinvention, gas phase doping is selectively used to provide simultaneousdoping of polysilicon gates and SID regions. In particular in thisembodiment, the gate stack 20 and well 18 that are not going to be dopedare covered by an appropriate diffusion preventing material 40. Thisdiffusion preventing material 40 may be deposited by a variety ofmethods such as chemical vapor deposition (CVD), vapor deposition orsputtering. Further, the diffusion preventing material 40 can take avariety of forms. For instance, silicon nitride or silicon dioxide maybe used depending on the progression of the process. Next, in order todope the unmasked region, the S/D regions 19 and polysilicon gate 24 areexposed to a gaseous (or plasma) doping source 30 of a chosen type,i.e., n-type or p-type, while the entire device 10 is heated to atemperature greater than 800° C. depending on the dopant used. This gasmay take a variety of forms depending on the desired type of doping,i.e., p-type or n-type. For instance, arsenic trichloride (AsCl₃),arsenic triflouride (AsF₃), phosphine (PH₃), phosphorous trichloride(PCl₃), phosphorous triflouride (PF₃) and arsine (AsH₃) have been usedwith success as n-type gaseous dopants.

[0023] Generally, heating is provided by furnace heating. However, as analternative, only the region where the doping is made may be heated.This alternative may be provided while the wafer is exposed to thegaseous (or plasma) doping source 30, for example, by either a maskedlaser beam (not shown) or a rapid thermal anneal-type lamp (not shown).Of note, if a masked laser beam is used, the diffusion preventingmaterial 40 may not be needed.

[0024] Next, the diffusion preventing material 40 is removed and theprocess repeated for the remaining gate stacks 20 and S/D regions 19using the opposite type doping source, i.e., p-type or n-type, dependingon the first used doping source. Examples of p-type dopants that havebeen used are: diborane (B₂H₆), boro trichloride (BCl₃), and borotriflouride (BFF₃).

[0025] The above described method provides a narrow polysilicon gate,i.e., less than 0.2μ, that is doped from the sidewalls to ensure highdoping of the polysilicon gate body 24 through to the gate dielectricinterface, i.e., where the gate body 24 and dielectric layer 22 meet.Shallow S/D extension doping in the range of less than 0.1μ deep is alsoachieved without extra lateral scattering of dopant experienced indoping by an ion implantation.

[0026] A second embodiment of the present invention involves the use ofsolid phase doping. In this embodiment, as illustrated in FIG. 3, afirst type dopant source material 150 is first deposited, for instanceby chemical vapor deposition (CVD), over a gate stack 120 and associatedSID region. This first type dopant material 150 may take a variety offorms. For example, boron doped silicate glass (BSG) may be used as ap-type dopant material. Next a thin diffusion preventing material 140 isdeposited. Again, this diffusion preventing material 140 may take avariety of forms, for example, silicon nitride or silicon dioxide.

[0027] The first type dopant material 150 and diffusion preventingmaterial 140 are then patterned (e.g., by applying a photoresist (notshown), exposing, developing and etching) so that the first type dopantmaterial 150 is contacting only the SID region and polysilicon gate 124over the chosen well area, e.g., the n-well area 118. Next, a secondtype dopant source material 160, e.g., arsenic doped silicate glass(ASG) as an n-type dopant, is deposited over the entire device.

[0028] The device is then heated to drive the dopants from the twodopant source materials 150, 160 to the polysilicon and S/D regions.Alternatively, the order of the doping area, i.e., p-well or n-well, maybe switched. In particular, the first type dopant material 150 may be ann-type doping source material and a diffusion preventing layer 140 maybe deposited and patterned so that the n-type dopant material 150 iscontacting only the S/D region and gate stack 120 over the p-well area116. Further, the n-type dopant may be driven-in before a second p-typedoping source material is deposited. P-type doping source material wouldthen be deposited and the dopant driven-in. By this method, the junctiondepth can be controlled to be approximately the same for both dopingtypes. Again, the result is a very shallow S/D extension and a highlydoped polysilicon gate, i.e., greater than 10¹⁹ atoms of dopant/cm³,completely through to the gate dielectric interface.

[0029] In a third embodiment of the present invention, a combination ofsolid phase doping and gas (or plasma) phase doping is provided. Asillustrated in FIG. 4, a first area 10R, including a first S/D region219R and a polysilicon gate 224R, is doped from a solid doping source250 with a covering of diffusion preventing material 240. In particular,a first type dopant source material 250, such as BSG as a p-type dopant,and a thin diffusion preventing material 240, such as silicon nitride orsilicon dioxide, are deposited, patterned, and etched so that the firsttype dopant material 250 is contacting only the S/D region 219R and thepolysilicon gate stack 220R over the selected well 218 of the first area10R.

[0030] Simultaneously, a second area 10L including a second S/D region219L and polysilicon gate 224L are doped from a gas (or plasma) phase230 with the layer of diffusion preventing material 240 masking thefirst area 10R. The device is then heated to a temperature greater than800° C. while the S/D region 219L and the polysilicon gate stack 220Lover the second area 10L is exposed to the gas phase 230 such as Arsine(AsH₃). Again, as an alternative, the order of the type of doping area,i.e., p-well or n-well, may be switched. That is, an n-type dopingsource material, e.g., ASG, and diffusion preventing material 240, e.g.,silicon dioxide, may be deposited and patterned so that the n-typedopant material 250 is contacting only the SID region 219L andpolysilicon gate stack 220L over the p-well area 216. Further, then-type dopant may be driven-in before p-type doping is carried out bythe gas phase doping. Once again, the junction depths of both typedopants can be controlled to be approximately the same by this method,and the resulting semiconductor exhibits a highly doped polysilicon gate224L, i.e., greater than 10¹⁹ atoms of dopant/cm³, completely through tothe gate dielectric 222 interface and very shallow S/D extensions, i.e.,less than 0.1μ.

[0031] As a result of the above embodiments of the present invention,deep source/drain diffusion doping, i.e., greater than 0.1μ, is moreeasily facilitated. In particular, as shown in FIG. 5, after the narrowpolysilicon gate 324 and the S/D extensions 319 are doped, spacerforming material 342, such as silicon dioxide or silicon nitride, may bedeposited and etched to form the gate spacer 344. If solid doping sourcematerial is used, the doping source material, such as BSG 352, may beused to form a part of the spacer 344 as shown in FIG. 5.

[0032] Next, N+ or P+ ion implantation is performed with a blocking mask(not shown) covering the opposite type doping area to form deep SIDdiffusions 317, adjacent the shallower S/D diffusions 319. Widerpolysilicon gates (not shown) are also doped by this implantation.Dopants in this phase are activated by heating either by rapid thermalanneal (RTA) or conventional furnaces. The spacers are used to keep thedeep S/D diffusion 317 sufficiently away from the device gate edges 325in order to minimize the short channel effects. The deep S/D diffusion317 is needed to form silicide over the diffusion area without severejunction leakage and also to form diffusion contact without shorting tothe well.

[0033] After deep SID diffusion (>0.1μ) formation, as shown in FIG. 6,silicide 480 (salicide) is selectively formed over the diffusions 417,419. The type of silicide formed may take a variety of forms, forinstance, TiSi, or CoSi_(x). Insulation material 482 is then depositedto fill the gap between and over the gate stacks 420. The insulationmaterial 482 may also take a variety of forms, e.g., silicon dioxide orsilicon nitride. A preferred material for this step being silicondioxide.

[0034] This insulation material 482 may then be planarized by apolishing/removal, for instance, by chemical mechanical polishing (CMP).Contact holes 484 are then etched through the insulation material 482 tothe S/D diffusions 417. The contact holes 484 are filled by highlyconductive material 486. This material may take the form of any highlyconductive material, for instance, tungsten (W), tungsten silicide(WSi_(x)), titanium silicide (TiSi_(x)), molybdenum (Mo), molybdenumsilicide (MoSi_(x)), or heavily doped polysilicon. The highly conductivematerial 486 is then planarized, e.g., by CMP, to form a contact plug488. Then, first level metal line 490 is formed over the contact plug488 to wire the Field Effect Transistor (FET) device into a desiredcircuit (not shown).

[0035]FIGS. 7 and 8 disclose a fourth embodiment of the presentinvention. Here, a gate stack 520 is formed and doped for one type ofdevice and then a gate stack 520 of the other device type is formed anddoped by the process of this embodiment. The rest of the process stepsare the same as for the first embodiment described above and will not berepeated here.

[0036] After formation of the gate stacks 520, i.e., layering of gatedielectric 522, polysilicon 524, highly conductive material 526 and adiffusion preventing layer 540, the gate stacks 520 are patterned andetched only over a first well area 518, e.g., the n-well area. Thisleaves a defined narrow gate stack 528 and a block of undefined gatestack 529 in the region where the other type of devices are built. Next,a first type doping source material 550, e.g., a p-type dopant such asBSG, and a diffusion preventing material 590 are deposited over theentire device. Deposition may be by a variety of forms, for instance,CVD. This is followed by the driving in of the dopant by conventionalheating methods.

[0037] Next, as shown in FIG. 8, the gate stack 529 over the second wellarea 516, e.g., the p-well area, is patterned and etched. A photoresist,not shown, may be added to cover the first well area 518. Next, theexposed gate polysilicon 524 over the second well area 516 is doped froma gas phase dopant 530 as described in the first embodiment.Alternatively, the order of the type of doping may be switched, i.e.,the gate stacks over the p-well area may be first patterned and etched,and diffusion extensions and gate polysilicon may be doped from ann-type gas phase dopant. After the n-type doping of the diffusionextension and gate polysilicon, a diffusion preventing layer isdeposited. Next, the gate stacks over the second well area are patternedand etched, and diffusion extensions and gate polysilicon are doped fromeither a gas phase dopant or a solid phase dopant. From this point, widegate stack and deep S/D diffusion doping followed by contact holecreation and wiring may take place, as described above and not repeatedhere for brevity sake.

[0038] The present invention also includes the resulting semiconductor.As is evident from the discussion of the methods above, the resultingsemiconductor exhibits unique structural characteristics not previouslyachievable. In particular, the resulting semiconductor has a narrowpolysilicon gate 24, e.g., less than 0.2μ, that is also highly dopedcompletely through to the gate dielectric interface (see FIG. 1). Thedegree of doping or consistency of the polysilicon gate is greater than10¹⁹ atoms of dopant/cm³. Furthermore, the resulting semiconductor hasvery shallow S/D extensions of less than 0.1μ in depth.

[0039] While this invention has been described in conjunction with thespecific embodiments outlined above, it is evident that manyalternatives, modifications and variations will be apparent to thoseskilled in the art. Accordingly, the preferred embodiments of theinvention as set forth above are intended to be illustrative, notlimiting. Various changes may be made without departing from the spiritand scope of the invention as defined in the following claims. Forexample in the second embodiment, the first type dopant can be done bygas phase doping or the first dopant may be an n-type dopant instead ofp-type. Further, it will be understood by one having ordinary skill inthe art that various modifications in the particular materials used maybe made without departing from the scope of the invention.

We claim:
 1. A method of doping a semiconductor comprising the steps of:a) providing a layer including at least one gate stack and at least onesource-drain region; and b) simultaneously doping at least one gatestack and at least one source-drain region.
 2. The method of claim 1,wherein the step of providing a layer further includes forming the atleast one gate stack with a dielectric layer and a polysilicon gatebody, each gate stack including sidewalls.
 3. The method of claim 2,wherein the step of simultaneously doping includes the step of dopingeach polysilicon gate body through the sidewalls.
 4. The method of claim2, wherein the step of providing a layer further includes forming the atleast one gate stack with a conductor layer.
 5. The method of claim 1,wherein the step of simultaneously doping includes exposing at least onegate stack and at least one source-drain region to one of a gascontaining a selected first dopant and a plasma containing a selectedfirst dopant; and heating the semiconductor.
 6. The method of claim 5,further comprising the step of simultaneously exposing any remaininggate stacks and any remaining source-drain regions to one of a gascontaining a selected second dopant and a plasma containing a selectedsecond dopant; and heating the semiconductor.
 7. The method of claim 6,wherein the first dopant is one of a p-type dopant material and ann-type dopant material, and the second dopant is the other of a p-typedopant material and an n-type dopant material.
 8. The method of claim 7,wherein the n-type dopant material is one of arsenic trichloride,arsine, arsenic triflouride, phosphine, phosphorous trichloride, andphosphorous triflouride; and the p-type dopant material is one ofdiborane, boro trichloride, and boro triflouride.
 9. The method of claim1, wherein the step of simultaneously doping further includes: b1)depositing a first type dopant source material across at least one gatestack and at least one of the source-drain region; b2) depositing adiffusion preventing material across the first type dopant sourcematerial; b3) depositing a second type dopant source material across anygate stacks and any source-drain regions not covered by the first typedopant source material; and b4) heating the semiconductor to drive indopants of the dopant source materials.
 10. The method of claim 9,wherein the first type dopant material is one of arsenic doped silicateglass and boron doped silicate glass, and the second type dopantmaterial is the other of arsenic of arsenic doped silicate glass andboron doped silicate glass.
 11. The method of claim 1, wherein the stepof simultaneously doping includes: b1) depositing a first type dopantsource material across at least one gate stack and at least onesource-drain region; b2) depositing a diffusion preventing materialacross the first type dopant source material; b3) simultaneously heatingthe device to drive in dopants of the first type dopant source materialsand exposing any remaining gate stacks and any remaining source-drainregions not covered by the first type dopant source material anddiffusion preventing material to one of a gas containing a selectedsecond type dopant material and a plasma containing a selected secondtype dopant material.
 12. The method of claim 11, wherein the first typedopant material is one of a p-type dopant material and a n-type dopantmaterial, and the second type dopant material is the other of the p-typedopant material and the n-type dopant material.
 13. The method of claim11, wherein the first type dopant source material is arsenic dopedsilicate glass; and the second type dopant material is one of diborane,boro trichloride, and boro triflouride.
 14. The method of claim 11,wherein the first type dopant material is boron doped silicate glass;and the second type dopant material is one of arsenic trichloride,arsine, arsenic triflouride, phosphine, phosphorous trichloride, andphosphorous triflouride.
 15. The method of claim 1, wherein the step ofproviding a layer includes providing a gate stack with a width of lessthan 0.2 micrometer.
 16. A method of forming a semiconductor comprisingthe steps of: a) providing a layer for a semiconductor; b) creating atleast one gate stack on the layer; c) creating at least one source-drainregion in the layer; and d) simultaneously doping at least one gatestack and at least one source-drain region.
 17. The method of claim 16,further including the step of creating a plurality of shallow isolationtrenches in the layer prior to step b).
 18. The method of claim 16,wherein step b) further includes forming each gate stack with adielectric layer and a polysilicon gate body, each gate stack includingsidewalls.
 19. The method of claim 18, wherein step b) further includesforming each gate stack with a conductor layer.
 20. The method of claim16, wherein the step of simultaneously doping includes the step ofdoping the polysilicon gate body through the sidewalls.
 21. The methodof claim 16, wherein the step of simultaneously doping includes exposingat least one gate stack and at least one source-drain region to one of agas containing a selected first dopant and a plasma containing aselected first dopant; and heating the semiconductor.
 22. The method ofclaim 21, further comprising the step of simultaneously exposing anyremaining gate stacks and any remaining source-drain regions to one of agas containing a selected second dopant and a plasma containing aselected second dopant; and heating the semiconductor.
 23. The method ofclaim 16, wherein the step of simultaneously doping includes: d1)depositing a first type dopant source material across at least one gatestack and at least one source-drain region; d2) depositing a diffusionpreventing material across the first type dopant source material; d3)depositing a second type dopant source material across any remaininggate stacks and any remaining source-drain regions not covered by thefirst type dopant source material; and d4) heating the device to drivein dopants of the first and second type dopant source materials.
 24. Themethod of claim 16, wherein the step of simultaneously doping includes:d1) depositing a first type dopant source material across at least onegate stack and at least one source-drain region; d2) depositing adiffusion preventing material across the first type dopant sourcematerial; d3) simultaneously heating the device to drive in dopants ofthe first type dopant source material and exposing any remaining gatestacks and any remaining source-drain regions not covered by the firsttype dopant source material and diffusion preventing material to one ofa gas containing a selected second dopant and a plasma containing aselected second dopant.
 25. The method of claim 16, wherein the step ofcreating at least one gate stack on the layer includes providing atleast one polysilicon gate body with a width of less than 0.2micrometer.
 26. A semiconductor comprising: a source-drain extensionarea with a depth of less than 0.1 micrometers.
 27. A semiconductorcomprising: a gate dielectric portion; and a polysilicon gate coupled tothe gate dielectric portion at an interface, the polysilicon gate havinga consistency of dopant material greater than 10¹⁹ atoms of dopantmaterial per cubic centimeter completely through to the interface withthe gate dielectric.
 28. The semiconductor of claim 27, wherein thepolysilsicon gate has a width of less than 0.2 micrometers.
 29. Thesemiconductor of claim 27, wherein the semiconductor further includes asource-drain extension having a depth of less than 0.1 micrometer.